PIC18F2331/2431/4331/4431
3.6.2
INTRC OUTPUT FREQUENCY
3.6
Internal Oscillator Block
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
This changes the frequency of the INTRC source from
its nominal 31.25 kHz. Peripherals and features that
depend on the INTRC source will be affected by this
shift in frequency.
The PIC18F2331/2431/4331/4431 devices include an
internal oscillator block, which generates two different
clock signals; either can be used as the system’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
3.6.3
OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at the
factory, but can be adjusted in the user’s application.
This is done by writing to the OSCTUNE register
(Register 3-1). Each increment may adjust the FRC
frequency by varying amounts and may not be mono-
tonic. The next closest frequency may be multiple steps
apart.
The other clock source is the internal RC oscillator
(INTRC), which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source, or when any of the
following are enabled:
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred. Oper-
ation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
3.6.4
INTOSC FREQUENCY DRIFT
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 3-2).
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz. This frequency, however, may
drift as the VDD or temperature changes, which can
affect the controller operation in a variety of ways.
3.6.1
INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
The INTOSC frequency can be adjusted by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make an adjustment, in which direction it should be
made, and in some cases, how large a change is
needed. Three compensation techniques are discussed
in Section 3.6.4.1 “Compensating with the
EUSART”, Section 3.6.4.2 “Compensating with the
Timers” and Section 3.6.4.3 “Compensating with the
CCP Module in Capture Mode”, but other techniques
may be used.
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
DS39616D-page 32
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
