PIC18FXX20
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Flag Registers (PIR1, PIR2 and PIR3).
2: User software should ensure the appropriate
interrupt flag bits are cleared prior to enabling
an interrupt, and after servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
RC1IF
R-0
TX1IF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RC1IF: USART1 Receive Interrupt Flag bit
1= The USART1 receive buffer, RCREG, is full (cleared when RCREG is read)
0= The USART1 receive buffer is empty
TX1IF: USART Transmit Interrupt Flag bit
1= The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The USART1 transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= MR1 register did not overflow
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39609A-page 92
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
