PIC18FXX20
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
8
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L)+
16
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
16
(ARG1H • ARG2H • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
)
8
8
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L)
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L,
ARG2L
W
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
;
;
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
;
;
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1H,
ARG2H
W
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H,
ARG2H
W
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L,
ARG2H
W
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
PRODL,
RES1,
PRODH,
W
F
W
F
;
MOVF
MULWF
ARG1L,
ARG2H
W
; Add cross
; products
;
;
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
PRODL,
RES1,
PRODH,
W
F
W
F
F
W
;
MOVF
MULWF
ARG1H,
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
F
W
;
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
PRODL,
RES1,
PRODH,
W
F
W
F
MOVF
MULWF
ARG1H,
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
PRODL,
RES1,
PRODH,
W
F
W
F
F
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H,
SIGN_ARG1
ARG1L,
RES2
ARG1H,
7
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
F
W
W
SUBWFB RES3
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
SIGN_ARG1
BTFSS
BRA
ARG1H,
CONT_CODE
ARG2L,
RES2
ARG2H,
7
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
W
W
SUBWFB RES3
;
CONT_CODE
:
DS39609A-page 86
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
