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PIC18LF6620-I/PT 参数 Datasheet PDF下载

PIC18LF6620-I/PT图片预览
型号: PIC18LF6620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
the holding registers are written. At the end of updating  
8 registers, the EECON1 register must be written to, to  
start the programming operation with a long write.  
The long write is necessary for programming the inter-  
nal FLASH. Instruction execution is halted while in a  
long write cycle. The long write will be terminated by  
the internal programming timer.  
The EEPROM on-chip timer controls the write time.  
The write/erase voltages are generated by an on-chip  
charge pump, rated to operate over the voltage range  
of the device for byte or word operations.  
5.5  
Writing to FLASH Program  
Memory  
The minimum programming block is 4 words or 8 bytes.  
Word or byte programming is not supported.  
Table Writes are used internally to load the holding reg-  
isters needed to program the FLASH memory. There  
are 8 holding registers used by the Table Writes for  
programming.  
Since the Table Latch (TABLAT) is only a single byte,  
the TBLWT instruction has to be executed 8 times for  
each programming operation. All of the Table Write  
operations will essentially be short writes, because only  
FIGURE 5-5:  
TABLE WRITES TO FLASH PROGRAM MEMORY  
TABLAT  
Write Register  
8
8
8
8
TBLPTR = xxxxx0  
TBLPTR = xxxxx2  
TBLPTR = xxxxx7  
TBLPTR = xxxxx1  
Holding Register  
Holding Register  
Holding Register  
Holding Register  
Program Memory  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 67