PIC18FXX20
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
Details
on
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
page:
CMCON
C2OUT
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
IBF
USART1 Baud Rate Generator
USART1 Receive Register
USART1 Transmit Register
CSRC
SPEN
—
Data EEPROM Address Register
Data EEPROM Data Register
Data EEPROM Control Register 2 (not a physical register)
EEPGD
—
—
—
—
—
—
PSPIP
PSPIF
PSPIE
EBDIS
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 34, 223
xxxx xxxx 34, 143
xxxx xxxx 34, 143
TMR3H
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
T3CCP2
OBF
T3CKPS1 T3CKPS0
IBOV
T3CCP1
—
T3SYNC
—
TMR3CS TMR3ON 0000 0000 34, 143
PSPMODE
—
—
0000 ---- 34, 129
0000 0000 34, 205
0000 0000 34, 207
0000 0000 34,205
0000 -010 34, 198
0000 000x 34, 199
TX9
RX9
—
TXEN
SREN
—
SYNC
CREN
—
—
ADDEN
—
BRGH
FERR
—
TRMT
OERR
TX9D
RX9D
EE Adr Register High ---- --00 34, 83
0000 0000 34, 83
0000 0000 34, 83
---- ---- 34, 83
00-0 x000 34, 80
CFGS
—
—
—
RC2IP
RC2IF
RC2IE
—
—
—
RCIP
RCIF
RCIE
WAIT1
FREE
TX2IP
TX2IF
TX2IE
EEIP
EEIF
EEIE
TXIP
TXIF
WRERR
TMR4IP
TMR4IF
TMR4IE
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
WREN
CCP5IP
CCP5IF
CCP5IE
LVDIP
LVDIF
LVDIE
CCP1IP
CCP1IF
CCP1IE
—
WR
RD
CCP4IP
CCP4IF
CCP4IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
CCP3IP --11 1111 35, 100
CCP3IF --00 0000 35, 94
CCP3IE --00 0000 35, 97
CCP2IP -1-1 1111 35, 99
CCP2IF -0-0 0000 35, 93
CCP2IE -0-0 0000 35, 96
TMR1IP 0111 1111 35, 98
TMR1IF 0000 0000 35, 92
TMR1IE 0000 0000 35, 95
—
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
—
TXIE
WAIT0
(3)
MEMCON
WM0
0-00 --00 35, 71
1111 1111 35, 127
1111 1111 35, 124
---1 1111 35, 121
1111 1111 35, 119
1111 1111 35, 116
1111 1111 35, 113
1111 1111 35, 109
1111 1111 35, 106
-111 1111 35, 103
xxxx xxxx 35, 127
xxxx xxxx 35, 124
---x xxxx 35, 121
xxxx xxxx 35, 119
xxxx xxxx 35, 116
xxxx xxxx 35, 111
xxxx xxxx 35, 109
xxxx xxxx 35, 106
(3)
TRISJ
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
(3)
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
—
—
—
Data Direction Control Register for PORTG
Data Direction Control Register for PORTF
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
(1)
—
TRISA6
Data Direction Control Register for PORTA
(3)
LATJ
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
(3)
LATH
LATG
LATF
LATE
LATD
LATC
LATB
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609A-page 54
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
