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PIC18LF6620-I/PT 参数 Datasheet PDF下载

PIC18LF6620-I/PT图片预览
型号: PIC18LF6620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
T0CON (Timer0 Control) ..........................................131  
T1CON (Timer 1 Control) .........................................135  
T2CON (Timer 2 Control) .........................................141  
T3CON (Timer3 Control) ..........................................143  
T4CON (Timer4 Control) ..........................................147  
TXSTAx (Transmit Status and Control) ....................198  
WDTCON (Watchdog Timer Control) .......................250  
RESET ............................................................... 29, 239, 289  
MCLR Reset ...............................................................29  
MCLR Reset during SLEEP .......................................29  
Power-on Reset (POR) ..............................................29  
Programmable Brown-out Reset (PBOR) ..................29  
RESET Instruction ......................................................29  
Stack Full Reset .........................................................29  
Stack Underflow Reset ...............................................29  
Watchdog Timer (WDT) Reset ...................................29  
RESET, Watchdog Timer, Oscillator Start-up Timer,  
Power-up Timer and Brown-out Reset  
Requirements ...........................................................326  
RETFIE ............................................................................290  
RETLW .............................................................................290  
RETURN ..........................................................................291  
Return Address Stack  
and Associated Registers ..........................................43  
Revision History ...............................................................347  
RLCF ................................................................................291  
RLNCF .............................................................................292  
RRCF ...............................................................................292  
RRNCF .............................................................................293  
SS .................................................................................... 157  
SSP  
TMR2 Output for Clock Shift .............................141, 142  
TMR4 Output for Clock Shift .................................... 148  
SSPOV Status Flag ......................................................... 187  
SSPSTAT Register  
R/W Bit ..............................................................170, 171  
STATUS Bits  
Significance and Initialization Condition for  
RCON Register .................................................. 31  
SUBFWB ......................................................................... 294  
SUBLW ............................................................................ 295  
SUBWF ............................................................................ 295  
SUBWFB ......................................................................... 296  
SWAPF ............................................................................ 296  
T
Table Pointer Operations (table) ........................................ 64  
TBLRD ............................................................................. 297  
TBLWT ............................................................................. 298  
Time-out in Various Situations ........................................... 31  
Timer0 .............................................................................. 131  
16-bit Mode Timer Reads and Writes ...................... 133  
Associated Registers ............................................... 133  
Clock Source Edge Select (T0SE Bit) ..................... 133  
Clock Source Select (T0CS Bit) ............................... 133  
Operation ................................................................. 133  
Overflow Interrupt .................................................... 133  
Prescaler. See Prescaler, Timer0  
Timer0 and Timer1 External Clock  
S
Requirements .......................................................... 327  
Timer1 .............................................................................. 135  
16-bit Read/Write Mode ........................................... 138  
Associated Registers ............................................... 139  
Operation ................................................................. 136  
Oscillator ...........................................................135, 137  
Overflow Interrupt .............................................135, 138  
Special Event Trigger (CCP) ............................138, 152  
TMR1H Register ...................................................... 135  
TMR1L Register ....................................................... 135  
Use as a Real-Time Clock ....................................... 138  
Timer2 .............................................................................. 141  
Associated Registers ............................................... 142  
Operation ................................................................. 141  
Postscaler. See Postscaler, Timer2  
SCI. See USART  
SCK ..................................................................................157  
SDI ...................................................................................157  
SDO .................................................................................157  
Serial Clock, SCK .............................................................157  
Serial Communication Interface. See USART  
Serial Data In, SDI ...........................................................157  
Serial Data Out, SDO .......................................................157  
Serial Peripheral Interface. See SPI  
SETF ................................................................................293  
Slave Select, SS ..............................................................157  
SLEEP .............................................................. 239, 252, 294  
Software Simulator (MPLAB SIM) ....................................302  
Special Event Trigger. See Compare  
Special Features of the CPU ............................................239  
Configuration Registers .................................... 241249  
Special Function Registers ................................................47  
Map ............................................................................50  
SPI  
Serial Clock ..............................................................157  
Serial Data In ...........................................................157  
Serial Data Out .........................................................157  
Slave Select .............................................................157  
SPI Mode .................................................................157  
SPI Master/Slave Connection ..........................................161  
SPI Module  
PR2 Register ....................................................141, 154  
Prescaler. See Prescaler, Timer2  
SSP Clock Shift ................................................141, 142  
TMR2 Register ......................................................... 141  
TMR2 to PR2 Match Interrupt ...................141, 142, 154  
Timer3 .............................................................................. 143  
Associated Registers ............................................... 145  
Operation ................................................................. 144  
Oscillator ...........................................................143, 145  
Overflow Interrupt .............................................143, 145  
Special Event Trigger (CCP) ................................... 145  
TMR3H Register ...................................................... 143  
TMR3L Register ....................................................... 143  
Associated Registers ...............................................165  
Bus Mode Compatibility ...........................................165  
Effects of a RESET ..................................................165  
Master/Slave Connection .........................................161  
Slave Mode ..............................................................163  
SLEEP Operation .....................................................165  
DS39609A-page 358  
Advance Information  
2003 Microchip Technology Inc.