PIC18FXX20
To set up a Synchronous Slave Transmission:
18.4 USART Synchronous Slave Mode
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXxIE.
4. If 9-bit transmission is desired, set bit TX9.
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead
of being supplied internally in Master mode. TRISC<6>
must be set for this mode. This allows the device to
transfer or receive data while in SLEEP mode. Slave
mode is entered by clearing bit CSRC (TXSTAx<7>).
5. Enable the transmission by setting enable bit
TXEN.
18.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXxIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.
e) If enable bit TXxIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
RESETS
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
INTCON
GIE/
PEIE/
GIEL
ADIF
ADIE
ADIP
—
TMR0IE INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 0000
0000 0000
GIEH
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
—
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF 0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111
TX2IF TMR4IF CCP5IF
TX2IE TMR4IE CCP5IE CCP4IE
TX2IP TMR4IP CCP5IP CCP4IP
CCP4IF
CCP3IF
CCP3IE --00 0000
CCP3IP --11 1111
--00 0000
—
—
(1)
RCSTAx
TXREGx
SPEN
RX9
CREN ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 -010
0000 0000
(1)
USART Transmit Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SPBRGx
SYNC
—
BRGH
TRMT
TX9D
(1)
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates
the particular module. Bit names and RESET values are identical between modules.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 211
MICROCHIP [ MICROCHIP ]
