PIC18FXX20
Register 18-1 shows the layout of the Transmit Status
and Control Registers (TXSTAx) and Register 18-2
shows the layout of the Receive Status and Control
Registers (RCSTAx). USART1 and USART2 each
have their own independent and distinct pairs of trans-
mit and receive control registers, which are identical to
each other apart from their names. Similarly, each
USART has its own distinct set of transmit, receive and
baud rate registers.
18.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module (also known as a Serial
Communications Interface or SCI) is one of the two
types of serial I/O modules available on PIC18FXX20
devices. Each device has two USARTs, which can be
configured independently of each other. Each can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
Note: Throughout this section, references to reg-
ister and bit names that may be associated
with a specific USART module are referred
to generically by the use of ‘x’ in place of
the specific module number. Thus,
“RCSTAx” might refer to the receive status
register for either USART1 or USART2.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous - Master (half-duplex)
• Synchronous - Slave (half-duplex)
The pins of USART1 and USART2 are multiplexed with
the functions of PORTC (RC6/TX1/CK1 and
RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2), respectively. In order to configure
these pins as a USART:
• For USART1:
- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
• For USART2:
- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
- bit TRISG<1> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 197
MICROCHIP [ MICROCHIP ]
