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PIC18LF6620-I/PT 参数 Datasheet PDF下载

PIC18LF6620-I/PT图片预览
型号: PIC18LF6620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
WCOL Status Flag  
If the user writes the SSPBUF when a START  
sequence is in progress, the WCOL is set and the con-  
tents of the buffer are unchanged (the write doesn’t  
occur).  
17.4.8  
I2C MASTER MODE START  
CONDITION TIMING  
17.4.8.1  
To initiate a START condition, the user sets the START  
condition enable bit, SEN (SSPCON2<0>). If the SDA  
and SCL pins are sampled high, the baud rate genera-  
tor is reloaded with the contents of SSPADD<6:0> and  
starts its count. If SCL and SDA are both sampled high  
when the baud rate generator times out (TBRG), the  
SDA pin is driven low. The action of the SDA being  
driven low, while SCL is high, is the START condition  
and causes the S bit (SSPSTAT<3>) to be set. Follow-  
ing this, the baud rate generator is reloaded with the  
contents of SSPADD<6:0> and resumes its count.  
When the baud rate generator times out (TBRG), the  
SEN bit (SSPCON2<0>) will be automatically cleared  
by hardware, the baud rate generator is suspended,  
leaving the SDA line held low and the START condition  
is complete.  
Note: Because queueing of events is not  
allowed, writing to the lower 5 bits of  
SSPCON2 is disabled until the START  
condition is complete.  
Note: If at the beginning of the START condition,  
the SDA and SCL pins are already sam-  
pled low, or if during the START condition  
the SCL line is sampled low before the  
SDA line is driven low, a bus collision  
occurs, the Bus Collision Interrupt Flag,  
BCLIF is set, the START condition is  
aborted, and the I2C module is reset into its  
IDLE state.  
FIGURE 17-19:  
FIRST START BIT TIMING  
Set S bit (SSPSTAT<3>)  
Write to SEN bit occurs here  
SDA = 1,  
SCL = 1  
At completion of START bit,  
hardware clears SEN bit  
and sets SSPIF bit  
TBRG  
TBRG  
Write to SSPBUF occurs here  
2nd bit  
1st bit  
SDA  
TBRG  
SCL  
TBRG  
S
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 185  
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