PIC18F2220/2320/4220/4320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; disable interrupts
; required sequence
; write 55H
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write AAH
; start program (CPU stall)
NOP
BSF
INTCON,GIE
; re-enable interrupts
; loop until done
DECFSZ COUNTER_HI
GOTO
BCF
PROGRAM_LOOP
EECON1,WREN
; disable write to memory
6.5.2
WRITE VERIFY
6.6
Flash Program Operation During
Code Protection
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
See Section 23.0 “Special Features of the CPU”
(Section 23.5 “Program Verification and Code Pro-
tection”) for details on code protection of Flash
program memory.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset, during normal operation. In
these situations, users can check the WRERR bit and
rewrite the location.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on
Value on:
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
--00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
TABLAT
INTCON
EECON2
EECON1
IPR2
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
EEPROM Control Register 2 (not a physical register)
—
—
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
xx-0 x000 uu-0 u000
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
CCP2IP 11-1 1111 ---1 1111
CCP2IF 00-0 0000 ---0 0000
CCP2IE 00-0 0000 ---0 0000
PIR2
PIE2
Legend:
x= unknown, u= unchanged, r = reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
2003 Microchip Technology Inc.
DS39599C-page 79
MICROCHIP [ MICROCHIP ]
