PIC18F2220/2320/4220/4320
FIGURE 26-14:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
bit 6 - - - -1
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TSCH
Characteristic
Min
Max Units Conditions
71
SCK Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time PIC18FXX20
PIC18LFXX20
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TDOF
TSCR
SDO Data Output Fall Time
—
—
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
79
80
TSCF
SCK Output Fall Time (Master mode)
—
—
TSCH2DOV, SDO Data Output Valid after PIC18FXX20
TSCL2DOV SCK Edge
PIC18LFXX20
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
2003 Microchip Technology Inc.
DS39599C-page 333
MICROCHIP [ MICROCHIP ]
