PIC18F2220/2320/4220/4320
18.1 Asynchronous Operation in Power
Managed Modes
18.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART may operate in Asynchronous mode while
the peripheral clocks are being provided by the internal
oscillator block. This mode makes it possible to remove
the crystal or resonator that is commonly connected as
the primary clock on the OSC1 and OSC2 pins.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules available in the PIC18F2X20/4X20 family
of microcontrollers. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz. However, this frequency may
drift as VDD or temperature changes and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE regis-
ter to adjust the INTOSC output back to 8 MHz. Adjust-
ing the value in the OSCTUNE register allows for fine
resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The other method adjusts the value in the Baud Rate
Generator since there may be not be fine enough res-
olution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
The RC6/TX/CK and RC7/RX/DT pins must be config-
ured as shown for use with the Universal Synchronous
Asynchronous Receiver Transmitter:
• SPEN (RCSTA<7>) bit must be set (= 1)
• TRISC<7> bit must be set (= 1)
• TRISC<6> bit must be cleared (= 0)
Register 18-1 shows the Transmit Status and Control
register (TXSTA) and Register 18-2 shows the Receive
Status and Control register (RCSTA).
2003 Microchip Technology Inc.
DS39599C-page 195
MICROCHIP [ MICROCHIP ]
