PIC18F2220/2320/4220/4320
TABLE 3-3:
ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
Power
Activity During Wake-up from
Power Managed Mode
ClockReady
Status Bit
(OSCCON)
Clock in Power Primary System
Managed
Mode Exit
Delay
Managed Mode
Clock
Exit by Interrupt
CPU and peripherals
Exit by Reset
Not clocked or
LP, XT, HS
HSPLL
EC, RC, INTRC(1)
INTOSC(2)
LP, XT, HS
HSPLL
OSTS
Primary System
Clock
(PRI_IDLE mode)
clocked by primary clock Two-Speed Start-up
5-10 µs(5)
and executing
instructions.
(if enabled)(3)
.
—
IOFS
OST
CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until primary
clock source becomes
ready.
OSTS
OST + 2 ms
T1OSC or
INTRC(1)
EC, RC, INTRC(1) 5-10 µs(5)
—
INTOSC(2)
LP, XT, HS
HSPLL
1 ms(4)
IOFS
OST
OSTS
OST + 2 ms
INTOSC(2)
EC, RC, INTRC(1) 5-10 µs(5)
—
INTOSC(2)
LP, XT, HS
HSPLL
EC, RC, INTRC(1) 5-10 µs(5)
INTOSC(2) 1 ms(4)
None
OST
IOFS
Not clocked or
OSTS
Two-Speed Start-up (if
enabled) until primary
clock source becomes
OST + 2 ms
Sleep mode
—
ready(3)
.
IOFS
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
2003 Microchip Technology Inc.
DS39599C-page 39
MICROCHIP [ MICROCHIP ]
