PIC18F2220/2320/4220/4320
CONFIG2H (Configuration 2 High) .......................... 239
S
CONFIG2L (Configuration 2 Low) ............................ 239
CONFIG3H (Configuration 3 High) .......................... 240
CONFIG4L (Configuration 4 Low) ............................ 240
CONFIG5H (Configuration 5 High) .......................... 241
CONFIG5L (Configuration 5 Low) ............................ 241
CONFIG6H (Configuration 6 High) .......................... 242
CONFIG6L (Configuration 6 Low) ............................ 242
CONFIG7H (Configuration 7 High) .......................... 243
CONFIG7L (Configuration 7 Low) ............................ 243
CVRCON (Comparator Voltage
SCI. See USART.
SCK ................................................................................. 155
SDI ................................................................................... 155
SDO ................................................................................. 155
Serial Clock (SCK) Pin ..................................................... 155
Serial Communication Interface. See USART.
Serial Data In (SDI) Pin ................................................... 155
Serial Data Out (SDO) Pin ............................................... 155
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 289
Shoot-Through Current .................................................... 149
Slave Select (SS) Pin ...................................................... 155
SLEEP ............................................................................. 290
Sleep
Reference Control) ........................................... 227
Device ID Register 1 ................................................ 244
Device ID Register 2 ................................................ 244
ECCPAS (Enhanced CCP
Auto-Shutdown Control) ................................... 150
EECON1 (Data EEPROM Control 1) ................... 73, 82
INTCON (Interrupt Control) ........................................ 89
INTCON2 (Interrupt Control 2) ................................... 90
INTCON3 (Interrupt Control 3) ................................... 91
IPR1 (Peripheral Interrupt Priority 1) .......................... 96
IPR2 (Peripheral Interrupt Priority 2) .......................... 97
LVDCON (LVD Control) ........................................... 233
OSCCON (Oscillator Control) .................................... 26
OSCTUNE (Oscillator Tuning) ................................... 23
PIE1 (Peripheral Interrupt Enable 1) .......................... 94
PIE2 (Peripheral Interrupt Enable 2) .......................... 95
PIR1 (Peripheral Interrupt Request
OSC1 and OSC2 Pin States ...................................... 27
Software Simulator (MPLAB SIM) ................................... 300
Software Simulator (MPLAB SIM30) ............................... 300
Special Event Trigger. See Compare
(CCP Module)
Special Features of the CPU ........................................... 237
Special Function Registers ................................................ 61
Map ............................................................................ 61
SPI Mode
Associated Registers ............................................... 163
Bus Mode Compatibility ........................................... 163
Effects of a Reset .................................................... 163
Master in Power Managed Modes ........................... 163
Master Mode ............................................................ 160
Master/Slave Connection ......................................... 159
Registers ................................................................. 156
Serial Clock .............................................................. 155
Serial Data In ........................................................... 155
Serial Data Out ........................................................ 155
Slave in Power Managed Modes ............................. 163
Slave Mode .............................................................. 161
Slave Select ............................................................. 155
SPI Clock ................................................................. 160
SS .................................................................................... 155
SSP
(Flag) 1) ............................................................. 92
PIR2 (Peripheral Interrupt Request
(Flag) 2) ............................................................. 93
PWM1CON (Enhanced PWM Configuration) ........... 149
RCON (Reset Control) ......................................... 69, 98
RCSTA (Receive Status and Control) ...................... 197
2
SSPCON1 (MSSP Control 1, I C Mode) ................. 166
SSPCON1 (MSSP Control 1, SPI Mode) ................. 157
2
SSPCON2 (MSSP Control 2, I C Mode) ................. 167
2
SSPSTAT (MSSP Status, I C Mode) ....................... 165
SSPSTAT (MSSP Status, SPI Mode) ...................... 156
Status ......................................................................... 68
STKPTR (Stack Pointer) ............................................ 55
Summary .............................................................. 62–64
T0CON (Timer0 Control) .......................................... 117
T1CON (Timer 1 Control) ......................................... 121
T2CON (Timer 2 Control) ......................................... 127
T3CON (Timer3 Control) .......................................... 129
TRISE ...................................................................... 112
TXSTA (Transmit Status and Control) ..................... 196
WDTCON (Watchdog Timer Control) ....................... 246
Reset .......................................................................... 43, 285
Resets .............................................................................. 237
RETFIE ............................................................................ 286
RETLW ............................................................................. 286
RETURN .......................................................................... 287
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 54
Revision History ............................................................... 369
RLCF ................................................................................ 287
RLNCF ............................................................................. 288
RRCF ............................................................................... 288
RRNCF ............................................................................. 289
2
2
I C Mode. See I C.
SSPBUF Register .................................................... 160
SSPSR Register ...................................................... 160
TMR2 Output for Clock Shift .............................127, 128
SSPOV Status Flag ......................................................... 185
SSPSTAT Register
R/W Bit .............................................................168, 169
Stack Full/Underflow Resets .............................................. 55
SUBFWB ......................................................................... 290
SUBLW ............................................................................ 291
SUBWF ............................................................................ 291
SUBWFB ......................................................................... 292
SWAPF ............................................................................ 293
T
TABLAT Register ............................................................... 74
Table Pointer Operations (table) ........................................ 74
Table Reads/Table Writes ................................................. 59
TBLPTR Register ............................................................... 74
TBLRD ............................................................................. 294
TBLWT ............................................................................. 295
Time-out in Various Situations (table) ................................ 45
Time-out Sequence ........................................................... 44
2003 Microchip Technology Inc.
DS39599C-page 379
MICROCHIP [ MICROCHIP ]
