PIC18F2220/2320/4220/4320
17.4.7
BAUD RATE
17.4.7.1
Baud Rate Generation in Power
Managed Modes
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
When the device is operating in a power managed
mode, the clock source to the Baud Rate Generator
may change frequency or stop, depending on the
power managed mode and clock source selected.
In most power modes, the Baud Rate Generator
continues to be clocked but may be clocked from the
primary clock (selected in a configuration word), the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the internal oscillator block (one of eight frequencies
between 31 kHz and 8 MHz). If the Sleep mode is
selected, all clocks are stopped and the Baud Rate
Generator will not be clocked.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Reload
Control
BRG Down Counter
CLKO
FOSC/4
TABLE 17-3: I2C CLOCK RATE W/BRG
SSPADD VALUE
(See Register 17-4,
Mode 1000)
(2)
FSCL
FOSC
FCY
FCY*2
(2 Rollovers of BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Bh
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
4 MHz
100kHz
1 MHz(1)
4 MHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2: Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low
time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”).
2003 Microchip Technology Inc.
DS39599C-page 181
MICROCHIP [ MICROCHIP ]
