PIC18F2220/2320/4220/4320
FIGURE 1-1:
PIC18F2220/2320 BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2>
21
21
Address Latch
Program Memory
(4 Kbytes)
Data Latch
20
inc/dec logic
8
8
8
8
Data Latch
Data RAM
(512 Bytes)
Address Latch
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-/CV
REF
RA3/AN3/V
REF
+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
OSC2/CLKO/RA6
(3)
OSC1/CLKI/RA7
(3)
PORTB
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2
(1)
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
PCLATU PCLATH
PCU PCH PCL
Program Counter
12
(2)
Address<12>
4
BSR
12
4
31 Level Stack
FSR0
Bank0, F
FSR1
FSR2
12
inc/dec
logic
16
Table Latch
8
ROM Latch
Decode
Instruction
Register
Instruction
Decode &
Control
3
8
PRODH PRODL
8 x 8 Multiply
OSC1
(3)
OSC2
(3)
T1OSI
T1OSO
Internal
Oscillator
Block
INT RC
Oscillator
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BIT OP
8
WREG
8
8
ALU<8>
8
PORTE
8
Precision
Voltage
Reference
RE3
(2)
MCLR
(2)
V
DD
, V
SS
Low-Voltage
Programming
In-Circuit
Debugger
Brown-out
Reset
Fail-Safe
Clock Monitor
Timer0
(8- or 16-bit)
Timer1
(16-bit)
Timer2
(8-bit)
Timer3
(16-bit)
10-bit A/D
Converter
CCP1
CCP2
Master
Synchronous
Serial Port
Addressable
USART
Data EEPROM
(256 Bytes)
Note
1:
Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 configuration bit.
2:
RE3 is available only when the MCLR Resets are disabled.
3:
OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to
for additional information.
2003 Microchip Technology Inc.
DS39599C-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
