PIC18F2220/2320/4220/4320
was executed and the INTOSC source was already
stable, the IOFS bit will remain set. If the IRCF bits are
all clear, the INTOSC output is not enabled and the
IOFS bit will remain clear; there will be no indication of
the current clock source.
3.3.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
When a wake-up event occurs, the peripherals con-
tinue to be clocked from the INTOSC multiplexer. After
a 10 µs delay following the wake-up event, the CPU
begins executing code, being clocked by the INTOSC
multiplexer. The microcontroller operates in RC_RUN
mode until the primary clock becomes ready. When the
primary clock becomes ready, a clock switch back to
the primary clock occurs (see Figure 3-8). When the
clock switch is complete, the IOFS bit is cleared, the
OSTS bit is set and the primary clock is providing the
system clock. The IDLEN and SCS bits are not affected
by the wake-up. The INTRC source will continue to run
if either the WDT or the Fail-Safe Clock Monitor is
enabled.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEPinstruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were previ-
ously at a non-zero value before the SLEEPinstruction
FIGURE 3-7:
TIMING TRANSITION TO RC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
2
3
4
5
6
7
8
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q4
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake-up from Interrupt Event
2003 Microchip Technology Inc.
DS39599C-page 35
MICROCHIP [ MICROCHIP ]
