PIC18F2220/2320/4220/4320
ANDWF
AND W with f
BC
Branch if Carry
[ label ] BC
Syntax:
[ label ] ANDWF
f [,d [,a]]
Syntax:
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
ANDWF
REG, W
Example:
Before Instruction
If No Jump:
Q1
W
REG
=
=
0x17
0xC2
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
After Instruction
W
REG
=
=
0x02
0xC2
HERE
BC JUMP
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
=
=
=
=
1;
PC
address (JUMP)
If Carry
PC
0;
address (HERE+2)
2003 Microchip Technology Inc.
DS39599C-page 263
MICROCHIP [ MICROCHIP ]
