PIC18F2220/2320/4220/4320
REGISTER 23-4: CONFIG3H:CONFIGURATIONREGISTER3HIGH(BYTEADDRESS300005h)
R/P-1
MCLRE
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
PBAD
R/P-1
CCP2MX
bit 0
bit 7
MCLRE: MCLR Pin Enable bit
1= MCLR pin enabled; RE3 input pin disabled
0= RE3 input pin enabled; MCLR disabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1
PBAD: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0>
pin configuration.)
1= PORTB<4:0> pins are configured as analog input channels on Reset
0= PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
CCP2MX: CCP2 Mux bit
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-5: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)
R/P-1
DEBUG
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVR
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6-3 Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1= Low-voltage ICSP enabled
0= Low-voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVR: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39599C-page 240
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
