PIC18F2220/2320/4220/4320
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
18.4.2
USART SYNCHRONOUS MASTER
RECEPTION
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
To set up a Synchronous Master Reception:
9. Read the 8-bit received data by reading the
RCREG register.
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
DS39599C-page 208
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
