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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
17.4.8  
I2C MASTER MODE START  
CONDITION TIMING  
17.4.8.1  
WCOL Status Flag  
If the user writes the SSPBUF when a Start sequence  
is in progress, the WCOL is set and the contents of the  
buffer are unchanged (the write doesn’t occur).  
To initiate a Start condition, the user sets the Start  
Condition Enable bit, SEN (SSPCON2<0>). If the SDA  
and SCL pins are sampled high, the Baud Rate Gener-  
ator is reloaded with the contents of SSPADD<6:0>  
and starts its count. If SCL and SDA are both sampled  
high when the Baud Rate Generator times out (TBRG),  
the SDA pin is driven low. The action of the SDA being  
driven low while SCL is high is the Start condition and  
causes the S bit (SSPSTAT<3>) to be set. Following  
this, the Baud Rate Generator is reloaded with the con-  
tents of SSPADD<6:0> and resumes its count. When  
the Baud Rate Generator times out (TBRG), the SEN bit  
(SSPCON2<0>) will be automatically cleared by  
hardware, the Baud Rate Generator is suspended,  
leaving the SDA line held low and the Start condition is  
complete.  
Note:  
Because queueing of events is not  
allowed, writing to the lower 5 bits of  
SSPCON2 is disabled until the Start  
condition is complete.  
Note:  
If at the beginning of the Start condition,  
the SDA and SCL pins are already sam-  
pled low or if during the Start condition, the  
SCL line is sampled low before the SDA  
line is driven low, a bus collision occurs,  
the Bus Collision Interrupt Flag, BCLIF, is  
set, the Start condition is aborted and the  
I2C module is reset into its Idle state.  
FIGURE 17-19:  
FIRST START BIT TIMING  
Set S bit (SSPSTAT<3>)  
At completion of Start bit,  
Write to SEN bit occurs here  
SDA = 1,  
SCL = 1  
hardware clears SEN bit  
and sets SSPIF bit  
TBRG  
TBRG  
Write to SSPBUF occurs here  
2nd bit  
1st bit  
SDA  
TBRG  
SCL  
TBRG  
S
2003 Microchip Technology Inc.  
DS39599C-page 183  
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