PIC18F2220/2320/4220/4320
When TMR1CS = 0, Timer1 increments every instruc-
12.1 Timer1 Operation
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. The TRISC1:TRISC0 values are
ignored and the pins read as ‘0’.
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
1
T1CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Prescaler
1, 2, 4, 8
(1)
FOSC/4
Internal
Clock
Oscillator
0
2
Peripheral Clocks
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
0
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
CLR
Timer 1
High Byte
TMR1L
Flag bit
1
TMR1ON
on/off
T1SYNC
T1OSC
T1CKI/T1OSO
1
Synchronize
Prescaler
1, 2, 4, 8
T1OSCEN
det
FOSC/4
Internal
Clock
Enable
0
(1)
T1OSI
Oscillator
2
Peripheral Clocks
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39599C-page 122
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
