PIC18F2220/2320/4220/4320
TABLE 10-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR/VPP/RE3
bit 0
ST/TTL(1)
Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1= PSP is Idle
0= Read operation. Reads PORTD register (if chip selected).
bit 1
bit 2
bit 3
ST/TTL(1)
ST/TTL(1)
ST
Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1= PSP is Idle
0= Write operation. Writes PORTD register (if chip selected).
Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1= PSP is Idle
0= External device is selected
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
(1)
PORTE
LATE
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
RE0
---- q000 ---- q000
---- -xxx ---- -uuu
0000 -111 0000 -111
LATE Data Latch Register
PORTE Data Direction bits
TRISE
IBF
—
OBF
—
IBOV
VCFG1
PSPMODE
VCFG0
—
ADCON1
Legend:
PCFG3
PCFG2
PCFG1
PCFG0 --00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0).
2003 Microchip Technology Inc.
DS39599C-page 113
MICROCHIP [ MICROCHIP ]
