欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC17LC42-16I/JW 参数 Datasheet PDF下载

PIC17LC42-16I/JW图片预览
型号: PIC17LC42-16I/JW
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS EPROM / ROM微控制器 [High-Performance 8-Bit CMOS EPROM/ROM Microcontroller]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 240 页 / 1141 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第116页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第117页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第118页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第119页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第121页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第122页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第123页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第124页  
PIC17C4X  
Compare f with WREG,  
DAW  
Decimal Adjust WREG Register  
[label] DAW f,s  
CPFSLT  
skip if f < WREG  
[ label ] CPFSLT  
0 f 255  
Syntax:  
Operands:  
Syntax:  
f
0 f 255  
Operands:  
Operation:  
s
[0,1]  
(f) – (WREG),  
skip if (f) < (WREG)  
(unsigned comparison)  
If [WREG<3:0> >9] .OR. [DC = 1] then  
WREG<3:0> + 6 f<3:0>, s<3:0>;  
else  
Operation:  
WREG<3:0> f<3:0>, s<3:0>;  
Status Affected:  
Encoding:  
None  
If [WREG<7:4> >9] .OR. [C = 1] then  
WREG<7:4> + 6 f<7:4>, s<7:4>  
else  
0011  
0000  
ffff  
ffff  
Compares the contents of data memory  
location 'f' to the contents of WREG by  
performing an unsigned subtraction.  
Description:  
WREG<7:4> f<7:4>, s<7:4>  
Status Affected:  
Encoding:  
C
If the contents of 'f' < the contents of  
WREG, then the fetched instruction is  
discarded and an NOP is executed  
instead making this a two-cycle instruc-  
tion.  
0010  
111s  
ffff  
ffff  
DAW adjusts the eight bit value in  
WREG resulting from the earlier addi-  
tion of two variables (each in packed  
BCD format) and produces a correct  
packed BCD result.  
Description:  
Words:  
Cycles:  
1
1 (2)  
s = 0: Result is placed in Data  
memory location 'f' and  
Q Cycle Activity:  
Q1  
WREG.  
Q2  
Q3  
Q4  
s = 1: Result is placed in Data  
memory location 'f'.  
Decode  
Read  
register 'f'  
Execute  
NOP  
Words:  
Cycles:  
1
1
If skip:  
Q1  
Q2  
Q3  
Q4  
Forced NOP  
NOP  
Execute  
NOP  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
HERE  
NLESS  
LESS  
CPFSLT REG  
Example:  
Decode  
Read  
Execute  
Write  
:
:
register 'f'  
register 'f'  
and other  
specified  
register  
Before Instruction  
PC  
W
=
=
Address (HERE)  
?
DAW  
REG1, 0  
Example1:  
After Instruction  
If REG  
PC  
If REG  
PC  
<
=
=
WREG;  
Address (LESS)  
WREG;  
Before Instruction  
WREG  
REG1  
C
=
=
=
=
0xA5  
??  
0
Address (NLESS)  
DC  
0
After Instruction  
WREG  
REG1  
C
=
=
=
=
0x05  
0x05  
1
DC  
0
Example 2:  
Before Instruction  
WREG  
REG1  
C
=
=
=
=
0xCE  
??  
0
DC  
0
After Instruction  
WREG  
REG1  
C
=
=
=
=
0x24  
0x24  
1
DC  
0
DS30412C-page 120  
1996 Microchip Technology Inc.  
 复制成功!