PIC17C75X
TABLRD
Table Read
TABLWT
Syntax:
Table Write
TABLRD 1, 1, REG ;
Example1:
[ label ] TABLWT t,i,f
Before Instruction
Operands:
0 ≤ f ≤ 255
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
i
t
[0,1]
[0,1]
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH;
TBLAT → Prog Mem
(TBLPTR);
If i = 1,
TBLPTR + 1 → TBLPTR
MEMORY(TBLPTR)
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0xAA
0x12
0x34
0xA357
0x5678
MEMORY(TBLPTR)
Status Affected:
Encoding:
None
TABLRD 0, 0, REG ;
Example2:
1010
11ti
ffff
ffff
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
1. Load value in ’f’ into 16-bit table
latch (TBLAT)
Description:
If t = 0: load into low byte;
If t = 1: load into high byte
MEMORY(TBLPTR)
2. The contents of TBLAT is written
to the program memory location
pointed to by TBLPTR
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x55
0x12
0x34
0xA356
0x1234
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
MEMORY(TBLPTR)
Note: The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be interrupted. A short write will occur (2 TCY).
The internal memory location will not be affected.
3. The TBLPTR can be automati-
cally incremented
If i = 0; TBLPTR is not
incremented
If i = 1; TBLPTR is incremented
Words:
1
Cycles:
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register
TBLATH or
TBLATL
No
No
No
No
operation
operation
(Table Pointer
on Address
bus)
operation
operation
(Table Latch on
Address bus,
WR goes low)
DS30264A-page 214
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
