PIC17C75X
INFSNZ
Syntax:
Increment f, skip if not 0
IORLW
Inclusive OR Literal with WREG
[ label ] IORLW k
0 ≤ k ≤ 255
[label] INFSNZ f,d
Syntax:
Operands:
0 ≤ f ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(WREG) .OR. (k) → (WREG)
Z
Operation:
(f) + 1 → (dest),
skip if not 0
1011
0011
kkkk
kkkk
Status Affected:
Encoding:
None
The contents of WREG are OR’ed with
the eight bit literal 'k'. The result is
placed in WREG.
0010
010d
ffff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead mak-
ing it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1(2)
IORLW
0x35
Example:
Q Cycle Activity:
Q1
Before Instruction
WREG
=
0x9A
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
After Instruction
WREG
=
0xBF
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
ZERO
NZERO
INFSNZ REG, 1
Example:
Before Instruction
REG
=
REG
After Instruction
REG
If REG
PC
If REG
PC
=
=
=
=
=
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
DS30264A-page 200
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
