欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F73-I/SO 参数 Datasheet PDF下载

PIC16F73-I/SO图片预览
型号: PIC16F73-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚, 8位CMOS闪存微控制器 [28/40-pin, 8-bit CMOS FLASH Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 174 页 / 3853 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
 浏览型号PIC16F73-I/SO的Datasheet PDF文件第57页浏览型号PIC16F73-I/SO的Datasheet PDF文件第58页浏览型号PIC16F73-I/SO的Datasheet PDF文件第59页浏览型号PIC16F73-I/SO的Datasheet PDF文件第60页浏览型号PIC16F73-I/SO的Datasheet PDF文件第62页浏览型号PIC16F73-I/SO的Datasheet PDF文件第63页浏览型号PIC16F73-I/SO的Datasheet PDF文件第64页浏览型号PIC16F73-I/SO的Datasheet PDF文件第65页  
PIC16F7X
9.0
9.1
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
SSP Module Overview
9.2
SPI Mode
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C)
An overview of I
2
C operations and additional informa-
tion on the SSP module can be found in the PICmicro™
Mid-Range
MCU
Family
Reference Manual
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I
2
C Multi-Master Environment”
(DS00578).
This section contains register definitions and opera-
tional characteristics of the SPI module. Additional
information on the SPI module can be found in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual (DS33023A).
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (IDLE state of SCK)
Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
2002 Microchip Technology Inc.
DS30325B-page 59