PIC16F913/914/916/917/946
TABLE 19-16: I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
400 kHz mode
Min.
Max.
Units
Conditions
0.6
1.5TCY
1.3
—
—
μs
Device must operate at a
minimum of 10 MHz
100*
THIGH
Clock high time
SSP Module
400 kHz mode
SSP Module
400 kHz mode
101*
TLOW
Clock low time
—
μs
Device must operate at a
minimum of 10 MHz
1.5TCY
20 + 0.1CB
—
102*
103*
90*
TR
SDA and SCL rise
time
250
ns
ns
μs
μs
CB is specified to be from
10-400 pF
TF
SDA and SCL fall time 400 kHz mode
20 + 0.1CB
250
—
CB is specified to be from
10-400 pF
TSU:STA
THD:STA
Start condition setup 400 kHz mode
time
1.3
0.6
Only relevant for Repeated
Start condition
91*
Start condition hold
time
400 kHz mode
—
After this period the first clock
pulse is generated
106*
107*
92*
THD:DAT
TSU:DAT
TSU:STO
Data input hold time
400 kHz mode
0
0.9
—
μs
ns
μs
Data input setup time 400 kHz mode
100
0.6
(Note 2)
(Note 1)
Stop condition setup
time
400 kHz mode
400 kHz mode
400 kHz mode
—
109*
110*
TAA
Output valid from
clock
—
—
—
ns
TBUF
Bus free time
1.3
μs
Time the bus must be free
before a new transmission
can start
CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode (400 kHz) I C bus device can be used in a Standard mode (100 kHz) I C bus system, but the requirement
TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
2
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL
line is released.
DS41250F-page 282
© 2007 Microchip Technology Inc.
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