PIC16F913/914/916/917/946
The AUSART module includes the following capabilities:
9.0
ADDRESSABLE UNIVERSAL
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Sleep operation
The
Addressable
Universal
Synchronous
Asynchronous Receiver Transmitter (AUSART)
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 9-1 and Figure 9-2.
FIGURE 9-1:
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
SPEN
Baud Rate Generator
FOSC
÷ n
TX9
n
+ 1
Multiplier x4 x16 x64
TX9D
SYNC
BRGH
1
x
0
1
0
0
SPBRG
© 2007 Microchip Technology Inc.
DS41250F-page 121
MICROCHIP [ MICROCHIP ]
