PIC16F913/914/916/917/946
FIGURE 3-29:
BLOCK DIAGRAM OF RF<7:0>
VDD
Data Bus
D
Q
Q
WR PORTF
CK
I/O Pin
VSS
Data Latch
D
Q
Q
WR TRISF
CK
TRIS Latch
SE<35:28> and LCDEN
SE<35:28> and LCDEN
RD TRISF
Schmitt
Trigger
RD PORTF
SEG<35:28>
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTF(1)
Value on all
other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDCON
LCDEN SLPEN
WERR
SE29
SE37
RF5
VLCDEN
SE28
CS1
SE27
SE35
RF3
CS0
SE26
SE34
RF2
LMUX1
SE25
LMUX0 0001 0011 0001 0011
(1)
LCDSE3
SE31
SE39
RF7
SE30
SE38
RF6
SE24
SE32
RF0
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
xxxx xxxx uuuu uuuu
(1)
LCDSE4
SE36
SE33
(1)
PORTF
RF4
RF1
(1)
TRISF
TRISF7 TRISF6 TRISF5
TRISF4
TRISF3 TRISF2
TRISF1
TRISF0 1111 1111 1111 1111
Legend:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by PORTF.
Note 1: PIC16F946 only.
© 2007 Microchip Technology Inc.
DS41250F-page 83
MICROCHIP [ MICROCHIP ]
