PIC16F913/914/916/917/946
3.2.1.8
RA7/OSC1/CLKIN/T1OSI
Figure 3-8 shows the diagram for this pin. The RA7 pin
is configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock input
• a Timer1 oscillator connection
FIGURE 3-8:
BLOCK DIAGRAM OF RA7
To OSC2
Oscillator
Circuit
FOSC = 011
Data Bus
D
Q
Q
WR PORTA
CK
VDD
VSS
Data Latch
D
Q
Q
I/O Pin
WR TRISA
CK
FOSC = 10x
TRIS Latch
FOSC = 10x
TTL
Input Buffer
RD TRISA
RD PORTA
TABLE 3-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
POR, BOR
Value on all
other Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
ANSEL
ADFM
ANS7
C2OUT
CPD
VCFG1
ANS6
C1OUT
CP
VCFG0
ANS5
CHS2
ANS4
CHS1
ANS3
CIS
CHS0
ANS2
CM2
GO/DONE
ANS1
ADON
ANS0
CM0
0000 0000
1111 1111
0000 0000
—
0000 0000
1111 1111
0000 0000
—
CMCON0
CONFIG(1)
C2INV
MCLRE
C1INV
PWRTE
CM1
WDTE
FOSC2
FOSC1
FOSC0
OPTION_REG
LCDCON
LCDSE0
LCDSE1
PORTA
RBPU
LCDEN
SE7
INTEDG
SLPEN
SE6
T0CS
WERR
SE5
T0SE
VLCDEN
SE4
PSA
CS1
PS2
CS0
PS1
LMUX1
SE1
PS0
LMUX0
SE0
1111 1111
0001 0011
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
1111 1111
0001 0011
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
1111 1111
SE3
SE2
SE15
RA7
SE14
SE13
RA5
SE12
RA4
SE11
RA3
SE10
RA2
SE9
SE8
RA6
RA1
RA0
SSPCON
T1CON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISA
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
See Configuration Word register (CONFIG) for operation of all register bits.
DS41250F-page 52
© 2007 Microchip Technology Inc.
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