PIC16F913/914/916/917/946
TABLE 2-2:
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
41,226
33,227
40,226
32,226
41,226
44,227
54,227
62,227
71,227
76,227
40,226
34,226
35,227
36,227
39,227
88,227
92,227
43,227
107,227
202,227
194,227
55,227
54,227
117,227
130,227
132,227
—
OPTION_REG
PCL
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
1111 1111
STATUS
FSR
PD
Z
DC
C
TRISA
TRISA7
TRISB7
TRISC7
TRISD7
TRISA6
TRISB6
TRISC6
TRISD6
TRISA5
TRISB5
TRISC5
TRISD5
TRISA4
TRISB4
TRISC4
TRISD4
TRISA3
TRISB3
TRISC3
TRISD3
TRISA2
TRISB2
TRISC2
TRISD2
TRISA1
TRISB1
TRISC1
TRISD1
TRISA0
TRISB0
TRISC0
TRISD0
TRISB
TRISC
TRISD(3)
TRISE
TRISE7(2) TRISE6(2) TRISE5(2) TRISE4(2) TRISE3(5) TRISE2(3) TRISE1(3) TRISE0(3) 1111 1111
PCLATH
INTCON
PIE1
—
GIE
—
PEIE
ADIE
C2IE
—
—
T0IE
RCIE
C1IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
0000 0000
INTE
TXIE
RBIE
SSPIE
—
T0IF
CCP1IE
LVDIE
—
INTF
TMR2IE
—
RBIF
EEIE
OSFIE
—
TMR1IE
CCP2IE(3) 0000 -0-0
PIE2
LCDIE
SBOREN
IRCF0
TUN4
PCON
—
POR
LTS
BOR
SCS
---1 --qq
-110 q000
---0 0000
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
0000 ----
---- --10
0000 -010
0000 0000
—
OSCCON
OSCTUNE
ANSEL
PR2
—
IRCF2
IRCF1
OSTS(4)
TUN3
ANS3
HTS
—
ANS7(3)
—
ANS6(3)
—
ANS5(3)
TUN2
ANS2
TUN1
ANS1
TUN0
ANS0
ANS4
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
SSPADD
SSPSTAT
WPUB
IOCB
SMP
WPUB7
IOCB7
—
CKE
WPUB6
IOCB6
—
D/A
WPUB5
IOCB5
—
P
S
WPUB3
—
R/W
WPUB2
—
UA
WPUB1
—
BF
WPUB0
—
WPUB4
IOCB4
—
CMCON1
TXSTA
SPBRG
—
—
—
T1GSS
TRMT
C2SYNC
TX9D
CSRC
TX9
TXEN
SYNC
—
BRGH
SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0
Unimplemented
Unimplemented
—
—
—
CMCON0
VRCON
ADRESL
ADCON1
C2OUT
VREN
C1OUT
—
C2INV
VRR
C1INV
—
CIS
CM2
VR2
CM1
VR1
CM0
VR0
0000 0000
0-0- 0000
xxxx xxxx
-000 ----
116,227
118,227
182,227
181,227
VR3
A/D Result Register Low Byte
ADCS2 ADCS1
—
ADCS0
—
—
—
—
Legend:
Note 1:
-= Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
PIC16F946 only, forced ‘0’ on PIC16F91X.
PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916.
The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.2 “Oscillator
Control”.
2:
3:
4:
5:
Bit is read-only; TRISE3 = 1always.
© 2007 Microchip Technology Inc.
DS41250F-page 29
MICROCHIP [ MICROCHIP ]
