PIC16F913/914/916/917/946
9.1.1.4
TSR Status
9.1.1.6
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
1. Initialize the SPBRG register and the BRGH bit to
achieve the desired baud rate (see Section 9.2
“AUSART Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
9.1.1.5
Transmitting 9-Bit Characters
The AUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
AUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
5. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
6. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
7. Load 8-bit data into the TXREG register. This
will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 9.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 9-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 9-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX/CK pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
TXIF bit
(Transmit Buffer
Empty Flag)
1 TCY
Word 1
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
DS41250F-page 124
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
