PIC16F913/914/916/917/946
FIGURE 4-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets(1)
CONFIG(2)
INTCON
OSCCON
OSCTUNE
PIE2
CPD
GIE
CP
PEIE
IRCF2
—
MCLRE
T0IE
IRCF1
—
PWRTE
INTE
WDTE
RBIE
OSTS
TUN3
—
FOSC2
T0IF
FOSC1
INTF
LTS
FOSC0
RBIF
—
—
0000 000x
-110 x000
---0 0000
0000 -0-0
0000 -0-0
0000 000x
-110 x000
---u uuuu
0000 -0-0
0000 -0-0
0000 0000
—
IRCF0
TUN4
LCDIE
LCDIF
HTS
SCS
—
TUN2
LVDIE
LVDIF
TUN1
—
TUN0
OSFIE
OSFIF
C2IE
C2IF
C1IE
C1IF
CCP2IE
CCP2IF
PIR2
—
—
T1CON
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
0000 0000
Legend:
Note 1:
2:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (CONFIG) for operation of all register bits.
DS41250F-page 98
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
