PIC16F87/88
7.1
Timer1 Operation
7.0
TIMER1 MODULE
Timer1 can operate in one of three modes:
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0>).
• as a Timer
• as a Synchronous Counter
• as an Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
The Timer1 oscillator can be used as a secondary clock
source in Low-power modes. When the T1RUN bit is
set along with SCS<1:0> = 01, the Timer1 oscillator is
providing the system clock. If the Fail-Safe Clock Mon-
itor is enabled, and the Timer1 oscillator fails while pro-
viding the system clock, polling the T1RUN bit will
indicate whether the clock is being provided by the
Timer1 oscillator or another source.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP1 module as
the special event trigger (see Section 9.1 “Capture
Mode”). Register 7-1 shows the Timer1 Control
register.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB6/T1OSO/T1CKI/PGC and RB7/T1OSI/
PGD pins become inputs. That is, the TRISB<7:6>
value is ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the PICmicro® Mid-Range MCU Family Reference
Manual (DS33023).
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 71