PIC16F882/883/884/886/887
FIGURE 4-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
POR, BOR
(1)
Resets
(2)
CONFIG1
CPD
—
CP
IRCF2
—
MCLRE PWRTE
WDTE
OSTS
TUN3
BCLIE
BCLIF
FOSC2
HTS
FOSC1
LTS
FOSC0
SCS
—
—
OSCCON
OSCTUNE
PIE2
IRCF1
—
IRCF0
TUN4
EEIE
EEIF
-110 x000 -110 x000
---0 0000 ---u uuuu
—
TUN2
TUN1
—
TUN0
OSFIE
OSFIF
C2IE
C2IF
C1IE
C1IF
ULPWUIE
ULPWUIF
CCP2IE 0000 00-0 0000 00-0
CCP2IF 0000 00-0 0000 00-0
PIR2
—
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word Register 1 (Register 14-1) for operation of all register bits.
41291D-page 72
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
