PIC16F882/883/884/886/887
2.2.2.7
PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0
OSFIF
bit 7
R/W-0
C2IF
R/W-0
C1IF
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
U-0
—
R/W-0
ULPWUIF
CCP2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= System clock operating
C2IF: Comparator C2 Interrupt Flag bit
1= Comparator output (C2OUT bit) has changed (must be cleared in software)
0= Comparator output (C2OUT bit) has not changed
C1IF: Comparator C1 Interrupt Flag bit
1= Comparator output (C1OUT bit) has changed (must be cleared in software)
0= Comparator output (C1OUT bit) has not changed
EEIF: EE Write Operation Interrupt Flag bit
1= Write operation completed (must be cleared in software)
0= Write operation has not completed or has not started
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision has occurred in the MSSP when configured for I2C Master mode
0= No bus collision has occurred
ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit
1= Wake-up condition has occurred (must be cleared in software)
0= No Wake-up condition has occurred
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
© 2007 Microchip Technology Inc.
Preliminary
DS41291D-page 35
MICROCHIP [ MICROCHIP ]
