PIC16F882/883/884/886/887
TABLE 11-6: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCP2CON
CCPR1L
CCPR1H
CCPR2L
CCPR2H
CM2CON1
INTCON
PIE1
P1M1
—
P1M0
—
DC1B1
DC2B1
DC1B0
DC2B0
CCP1M3
CCP2M3
CCP1M2
CCP2M2
CCP1M1
CCP2M1
CCP1M0
CCP2M0
0000 0000
--00 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 --10
0000 000x
-000 0000
0000 00-0
-000 0000
0000 00-0
0000 0000
xxxx xxxx
xxxx xxxx
1111 1111
0000 0000
--00 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 --10
0000 000x
-000 0000
0000 00-0
-000 0000
0000 00-0
0000 0000
xxxx xxxx
xxxx xxxx
1111 1111
Capture/Compare/PWM Register 1 Low Byte (LSB)
Capture/Compare/PWM Register 1 High Byte (MSB)
Capture/Compare/PWM Register 2 Low Byte (LSB)
Capture/Compare/PWM Register 2 High Byte (MSB)
MC1OUT
GIE
MC2OUT
PEIE
C1RSEL
T0IE
C2RSEL
INTE
TXIE
—
—
T1GSS
INTF
C2SYNC
RBIF
RBIE
T0IF
—
ADIE
RCIE
C1IE
SSPIE
BCLIE
SSPIF
BCLIF
CCP1IE
ULPWUIE
CCP1IF
ULPWUIF
T1SYNC
TMR2IE
—
TMR1IE
CCP2IE
TMR1IF
CCP2IF
TMR1ON
PIE2
OSFIE
—
C2IE
EEIE
TXIF
PIR1
ADIF
RCIF
C1IF
TMR2IF
—
PIR2
OSFIF
T1GINV
C2IF
EEIF
T1CON
TMR1L
TMR1H
TRISC
TMR1GE
T1CKPS1 T1CKPS0 T1OSCEN
TMR1CS
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture and
Compare.
TABLE 11-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
CCP1CON
CCP2CON
ECCPAS
INTCON
PR2
P1M1
—
P1M0
—
DC1B1
DC2B1
DC1B0
DC2B0
CCP1M3
CCP2M3
PSSAC1
RBIE
CCP1M2
CCP2M2
PSSAC0
T0IF
CCP1M1
CCP2M1
PSSBD1
INTF
CCP1M0
CCP2M0
PSSBD0
RBIF
0000 0000
--00 0000
0000 0000
0000 000x
1111 1111
---0 0001
0000 0000
0000 0000
--00 0000
0000 0000
0000 000x
1111 1111
---0 0001
0000 0000
-000 0000
0000 0000
1111 1111
1111 1111
1111 1111
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
GIE
PEIE
T0IE
INTE
Timer2 Period Register
PSTRCON
PWM1CON
T2CON
TMR2
—
PRSEN
—
—
—
STRSYNC
PDC4
STRD
PDC3
STRC
PDC2
STRB
PDC1
STRA
PDC0
PDC6
PDC5
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0 -000 0000
Timer2 Module Register
0000 0000
TRISB
TRISB7
TRISC7
TRISD7
TRISB6
TRISC6
TRISD6
TRISB5
TRISC5
TRISD5
TRISB4
TRISC4
TRISD4
TRISB3
TRISC3
TRISD3
TRISB2
TRISC2
TRISD2
TRISB1
TRISC1
TRISD1
TRISB0
TRISC0
TRISD0
1111 1111
1111 1111
1111 1111
TRISC
TRISD
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.
DS41291D-page 148
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
