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PIC16F886-I/SS 参数 Datasheet PDF下载

PIC16F886-I/SS图片预览
型号: PIC16F886-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,增强基于闪存的8位CMOS微控制器采用纳瓦技术 [28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 288 页 / 5120 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F882/883/884/886/887  
TABLE 11-2: CCP MODE – TIMER  
RESOURCES REQUIRED  
11.2 Capture/Compare/PWM (CCP2)  
The Capture/Compare/PWM module is a peripheral  
which allows the user to time and control different  
events. In Capture mode, the peripheral allows the  
timing of the duration of an event. The Compare mode  
allows the user to trigger an external event when a  
predetermined amount of time has expired. The PWM  
mode can generate a Pulse-Width Modulated signal of  
varying frequency and duty cycle.  
CCP Mode  
Timer Resource  
Capture  
Compare  
PWM  
Timer1  
Timer1  
Timer2  
The timer resources used by the module are shown in  
Table 11-2.  
Additional information on CCP modules is available in  
the Application Note AN594, “Using the CCP Modules”  
(DS00594).  
REGISTER 11-2: CCP2CON: CCP2 CONTROL REGISTER  
U-0  
U-0  
R/W-0  
R/W-0  
DC2B0  
R/W-0  
R/W-0  
R/W-0  
CCP2M1  
R/W-0  
DC2B1  
CCP2M3  
CCP2M2  
CCP2M0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7-6  
bit 5-4  
Unimplemented: Read as ‘0’  
DC2B<1:0>: PWM Duty Cycle Least Significant bits  
Capture mode:  
Unused.  
Compare mode:  
Unused.  
PWM mode:  
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR2L.  
bit 3-0  
CCP2M<3:0>: CCP2 Mode Select bits  
0000= Capture/Compare/PWM off (resets CCP2 module)  
0001= Unused (reserved)  
0010= Unused (reserved)  
0011= Unused (reserved)  
0100= Capture mode, every falling edge  
0101= Capture mode, every rising edge  
0110= Capture mode, every 4th rising edge  
0111= Capture mode, every 16th rising edge  
1000= Compare mode, set output on match (CCP2IF bit is set)  
1001= Compare mode, clear output on match (CCP2IF bit is set)  
1010= Compare mode, generate software interrupt on match (CCP2IF bit is set, CCP2 pin  
is unaffected)  
1011= Compare mode, trigger special event (CCP2IF bit is set, TMR1 is reset and A/D  
conversion is started if the ADC module is enabled. CCP2 pin is unaffected.)  
11xx= PWM mode.  
© 2007 Microchip Technology Inc.  
Preliminary  
DS41291D-page 125  
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