PIC16F87/88
• Clock before switch: One of INTOSC/INTOSC
4.6.6
OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND
CLOCK SWITCHING
postscaler (IRCF<2:0> ≠ 000)
1. IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
Table 4-3 shows the different delays invoked for vari-
ous clock switching sequences. It also shows the
delays invoked for POR and wake-up.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is set.
5. Oscillator switchover is complete.
TABLE 4-3:
OSCILLATOR DELAY EXAMPLES
Switch From Switch To
Frequency
Oscillator Delay
Comments
INTRC
T1OSC
31.25 kHz
32.768 kHz
SLEEP/POR INTOSC/
INTOSC
125 kHz - 8 MHz
Following a wake-up from SLEEP mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
5 µs - 10 µs (approx.)
CPU Start-up(1)
Postscaler
INTRC/SLEEP EC, RC
DC - 20 MHz
DC - 20 MHz
INTRC
EC, RC
(31.25 kHz)
SLEEP
LP, XT, HS 32.768 kHz - 20 MHz 1024 Clock Cycles Following a change from INTRC, an OST
(OST)
of 1024 cycles must occur.
INTRC
(31.25 kHz)
INTOSC/
INTOSC
125 kHz - 8 MHz
4 ms
Refer to Section 4.6.4 “Modifying the
IRCF bits” for further details.
Postscaler
Note 1: The 5 µs-10 µs start-up delay is based on a 1 MHz system clock.
DS30487B-page 42
Preliminary
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
