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PIC16F818-I/SS 参数 Datasheet PDF下载

PIC16F818-I/SS图片预览
型号: PIC16F818-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 二十零分之一十八引脚增强型闪存微控制器采用纳瓦技术 [18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 176 页 / 2941 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F818/819  
The CCP module’s input/output pin (CCP1) can be  
configured as RB2 or RB3. This selection is set in bit 12  
(CCPMX) of the Configuration Word register.  
9.0  
CAPTURE/COMPARE/PWM  
(CCP) MODULE  
The Capture/Compare/PWM (CCP) module contains a  
16-bit register that can operate as a:  
Additional information on the CCP module is available  
in the “PICmicro® Mid-Range MCU Family Reference  
Manual” (DS33023) and in Application Note AN594,  
Using the CCP Module(s)” (DS00594).  
16-bit Capture register  
16-bit Compare register  
PWM Master/Slave Duty Cycle register  
TABLE 9-1:  
CCP MODE – TIMER  
RESOURCE  
Table 9-1 shows the timer resources of the CCP  
module modes.  
CCP Mode  
Timer Resource  
Capture/Compare/PWM Register 1 (CCPR1) is com-  
prised of two 8-bit registers: CCPR1L (low byte) and  
CCPR1H (high byte). The CCP1CON register controls  
the operation of CCP1. The special event trigger is  
generated by a compare match which will reset Timer1  
and start an A/D conversion (if the A/D module is  
enabled).  
Capture  
Compare  
PWM  
Timer1  
Timer1  
Timer2  
REGISTER 9-1:  
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)  
U-0  
U-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
CCP1X  
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0  
bit 0  
bit 7  
bit 7-6  
bit 5-4  
Unimplemented: Read as ‘0’  
CCP1X:CCP1Y: PWM Least Significant bits  
Capture mode:  
Unused.  
Compare mode:  
Unused.  
PWM mode:  
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.  
bit 3-0  
CCP1M3:CCP1M0: CCP1 Mode Select bits  
0000= Capture/Compare/PWM disabled (resets CCP1 module)  
0100= Capture mode, every falling edge  
0101= Capture mode, every rising edge  
0110= Capture mode, every 4th rising edge  
0111= Capture mode, every 16th rising edge  
1000= Compare mode, set output on match (CCP1IF bit is set)  
1001= Compare mode, clear output on match (CCP1IF bit is set)  
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is  
unaffected)  
1011= Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);  
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)  
11xx= PWM mode  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
2004 Microchip Technology Inc.  
DS39598E-page 65