PIC16F818/819
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/AN4/T0CKI. The incrementing edge is determined
by the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.3 “Using Timer0 with
an External Clock”.
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt-on-overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 6.4
“Prescaler” details the operation of the prescaler.
Additional information on the Timer0 module is
available in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
6.2
Timer0 Interrupt
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit, TMR0IF (INTCON<2>). The interrupt can be
masked by clearing bit, TMR0IE (INTCON<5>). Bit
TMR0IF must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
6.1
Timer0 Operation
Timer0 operation is controlled through the
OPTION_REG register (see Register 2-2). Timer mode
is selected by clearing bit T0CS (OPTION_REG<5>).
In Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
FIGURE 6-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKO (= FOSC/4)
Data Bus
8
M
U
X
1
0
0
1
M
U
X
Sync
TMR0 reg
2
Cycles
RA4/AN4/T0CKI
pin
T0SE
T0CS
Set Flag bit TMR0IF
PSA
on Overflow
PRESCALER
0
1
8-bit Prescaler
M
U
X
WDT Timer
31.25 kHz
8
8-to-1 MUX
PS2:PS0
PSA
WDT Enable bit
1
0
PSA
MUX
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
2004 Microchip Technology Inc.
DS39598E-page 53
MICROCHIP [ MICROCHIP ]
