欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F818-I/SS 参数 Datasheet PDF下载

PIC16F818-I/SS图片预览
型号: PIC16F818-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 二十零分之一十八引脚增强型闪存微控制器采用纳瓦技术 [18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 176 页 / 2941 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F818-I/SS的Datasheet PDF文件第30页浏览型号PIC16F818-I/SS的Datasheet PDF文件第31页浏览型号PIC16F818-I/SS的Datasheet PDF文件第32页浏览型号PIC16F818-I/SS的Datasheet PDF文件第33页浏览型号PIC16F818-I/SS的Datasheet PDF文件第35页浏览型号PIC16F818-I/SS的Datasheet PDF文件第36页浏览型号PIC16F818-I/SS的Datasheet PDF文件第37页浏览型号PIC16F818-I/SS的Datasheet PDF文件第38页  
PIC16F818/819  
3.8  
Protection Against Spurious Write  
3.9  
Operation During Code-Protect  
There are conditions when the device should not write  
to the data EEPROM memory. To protect against  
spurious EEPROM writes, various mechanisms have  
been built-in. On power-up, WREN is cleared. Also, the  
Power-up Timer (72 ms duration) prevents an  
EEPROM write.  
When the data EEPROM is code-protected, the micro-  
controller can read and write to the EEPROM normally.  
However, all external access to the EEPROM is  
disabled. External write access to the program memory  
is also disabled.  
When program memory is code-protected, the micro-  
controller can read and write to program memory  
normally as well as execute instructions. Writes by the  
device may be selectively inhibited to regions of  
the memory depending on the setting of bits,  
WRT1:WRT0, of the Configuration Word (see  
Section 12.1 “Configuration Bits” for additional  
information). External access to the memory is also  
disabled.  
The write initiate sequence and the WREN bit together  
help prevent an accidental write during brown-out,  
power glitch or software malfunction.  
TABLE 3-1:  
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND  
FLASH PROGRAM MEMORIES  
Value on  
Power-on  
Reset  
Value on  
all other  
Resets  
Address Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
10Ch  
10Dh  
10Eh  
10Fh  
EEDATA EEPROM/Flash Data Register Low Byte  
EEADR EEPROM/Flash Address Register Low Byte  
xxxx xxxx uuuu uuuu  
xxxx xxxx uuuu uuuu  
--xx xxxx --uu uuuu  
---- -xxx ---- -uuu  
EEDATH  
EEADRH  
EEPROM/Flash Data Register High Byte  
EEPROM/Flash Address  
Register High Byte  
18Ch  
18Dh  
0Dh  
EECON1 EEPGD  
FREE WRERR WREN  
WR  
RD  
x--x x000 x--x q000  
---- ---- ---- ----  
---0 ---- ---0 ----  
---0 ---- ---0 ----  
EECON2 EEPROM Control Register 2 (not a physical register)  
PIR2  
PIE2  
EEIF  
EEIE  
8Dh  
Legend:  
x= unknown, u= unchanged, -= unimplemented, read as ‘0’, q= value depends upon condition.  
Shaded cells are not used by data EEPROM or Flash program memory.  
DS39598E-page 32  
2004 Microchip Technology Inc.  
 复制成功!