PIC16F818/819
2
SSPSTAT Register ............................................................ 14
Stack .................................................................................. 23
Overflow ..................................................................... 23
Underflow ................................................................... 23
Status Register ............................................................. 13, 15
DC Bit ......................................................................... 16
IRP Bit ........................................................................ 16
PD Bit ......................................................................... 91
TO Bit ................................................................... 16, 91
Z Bit ............................................................................ 16
Synchronous Serial Port (SSP) .......................................... 71
Overview .................................................................... 71
SPI Mode ................................................................... 71
Synchronous Serial Port Interrupt ...................................... 20
I C Bus Data ............................................................ 139
I C Bus Start/Stop Bits ............................................ 138
I C Reception (7-Bit Address) ................................... 78
I C Transmission (7-Bit Address) .............................. 78
PWM Output .............................................................. 68
Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer ............................................... 133
Slow Rise Time (MCLR Tied to VDD
2
2
2
Through RC Network) ........................................ 96
SPI Master Mode ....................................................... 75
SPI Master Mode (CKE = 0, SMP = 0) .................... 136
SPI Master Mode (CKE = 1, SMP = 1) .................... 136
SPI Slave Mode (CKE = 0) .................................75, 137
SPI Slave Mode (CKE = 1) .................................75, 137
Time-out Sequence on Power-up
T
T1CKPS0 Bit ...................................................................... 57
T1CKPS1 Bit ...................................................................... 57
T1OSCEN Bit ..................................................................... 57
T1SYNC Bit ........................................................................ 57
T2CKPS0 Bit ...................................................................... 64
T2CKPS1 Bit ...................................................................... 64
Tad ..................................................................................... 85
Time-out Sequence ............................................................ 92
Timer0 ................................................................................ 53
Associated Registers ................................................. 55
Clock Source Edge Select (T0SE Bit) ........................ 17
Clock Source Select (T0CS Bit) ................................. 17
External Clock ............................................................ 54
Interrupt ...................................................................... 53
Operation ................................................................... 53
Overflow Enable (TMR0IE Bit) ................................... 18
Overflow Flag (TMR0IF Bit) ....................................... 97
Overflow Interrupt ...................................................... 97
Prescaler .................................................................... 54
T0CKI ......................................................................... 54
Timer1 ................................................................................ 57
Associated Registers ................................................. 62
Capacitor Selection .................................................... 60
Counter Operation ..................................................... 58
Operation ................................................................... 57
Operation in Asynchronous
(MCLR Tied to VDD Through
Pull-up Resistor) ................................................ 95
Time-out Sequence on Power-up (MCLR
Tied to VDD Through RC Network): Case 1 ....... 95
Time-out Sequence on Power-up (MCLR
Tied to VDD Through RC Network): Case 2 ....... 95
Timer0 and Timer1 External Clock .......................... 134
Timer1 Incrementing Edge ........................................ 58
Wake-up from Sleep through Interrupt .................... 100
Timing Parameter Symbology ......................................... 130
Timing Requirements
External Clock .......................................................... 131
TMR0 Register ................................................................... 15
TMR1CS Bit ....................................................................... 57
TMR1H Register ................................................................ 13
TMR1L Register ................................................................. 13
TMR1ON Bit ...................................................................... 57
TMR2 Register ................................................................... 13
TMR2ON Bit ...................................................................... 64
TOUTPS0 Bit ..................................................................... 64
TOUTPS1 Bit ..................................................................... 64
TOUTPS2 Bit ..................................................................... 64
TOUTPS3 Bit ..................................................................... 64
TRISA Register .................................................................. 14
TRISB Register .............................................................14, 15
V
Counter Mode .................................................... 59
Operation in Synchronized
Vdd Pin ................................................................................ 8
Vss Pin ................................................................................. 8
Counter Mode .................................................... 58
Operation in Timer Mode ........................................... 58
Oscillator .................................................................... 60
Oscillator Layout Considerations ............................... 60
Prescaler .................................................................... 61
Resetting Register Pair (TMR1H, TMR1L) ................. 61
Resetting Using a CCP Trigger Output ...................... 61
TMR1H ....................................................................... 59
TMR1L ....................................................................... 59
Use as a Real-Time Clock ......................................... 61
Timer2 ................................................................................ 63
Associated Registers ................................................. 64
Output ........................................................................ 63
Postscaler .................................................................. 63
Prescaler .................................................................... 63
Prescaler and Postscaler ........................................... 63
Timing Diagrams
W
Wake-up from Sleep .....................................................89, 99
Interrupts ..............................................................93, 94
MCLR Reset .............................................................. 94
WDT Reset ................................................................ 94
Wake-up Using Interrupts .................................................. 99
Watchdog Timer (WDT) ................................................89, 98
Associated Registers ................................................. 98
Enable (WDTEN Bit) .................................................. 98
INTRC Oscillator ........................................................ 98
Postscaler. See Postscaler, WDT.
Programming Considerations .................................... 98
Time-out Period ......................................................... 98
WDT Reset, Normal Operation .......................91, 93, 94
WDT Reset, Sleep ................................................91, 94
WDT Wake-up ........................................................... 93
WCOL ................................................................................ 73
Write Collision Detect Bit, WCOL ...................................... 73
WWW, On-Line Support ...................................................... 3
A/D Conversion ........................................................ 142
Brown-out Reset ...................................................... 133
Capture/Compare/PWM (CCP1) .............................. 135
CLKO and I/O .......................................................... 132
External Clock .......................................................... 131
2004 Microchip Technology Inc.
DS39598E-page 169
MICROCHIP [ MICROCHIP ]
