PIC16F818/819
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The maximum recommended imped-
ance for analog sources is 2.5 kΩ. As the impedance
is decreased, the acquisition time may be decreased.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
EQUATION 11-1: ACQUISITION TIME
TACQ
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2 µs + TC + [(Temperature – 25°C)(0.05 µs/°C)]
= CHOLD (RIC + RSS + RS) In(1/2047)
= -120 pF (1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885)
= 16.47 µs
= 2 µs + 16.47 µs + [(50°C – 25°C)(0.05 µs/°C)
= 19.72 µs
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1K
RSS
RS
CHOLD
= DAC Capacitance
= 120 pF
CPIN
5 pF
VA
ILEAKAGE
± 500 nA
VT = 0.6V
VSS
Legend: CPIN
= input capacitance
= threshold voltage
6V
5V
VT
ILEAKAGE = leakage current at the pin due to
VDD 4V
3V
various junctions
= interconnect resistance
= sampling switch
2V
RIC
SS
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
DS39598D-page 84
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
