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PIC16F818-I/P 参数 Datasheet PDF下载

PIC16F818-I/P图片预览
型号: PIC16F818-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 二十零分之一十八引脚增强型闪存微控制器采用纳瓦技术 [18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 176 页 / 2941 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F818/819  
An SSP interrupt is generated for each data transfer  
byte. Flag bit SSPIF must be cleared in software and  
the SSPSTAT register is used to determine the status  
of the byte. Flag bit SSPIF is set on the falling edge of  
the ninth clock pulse.  
the data transfer is complete. When the ACK is latched  
by the slave device, the slave logic is reset (resets  
SSPSTAT register) and the slave device then monitors  
for another occurrence of the Start bit. If the SDA line  
was low (ACK), the transmit data must be loaded into  
the SSPBUF register which also loads the SSPSR  
register. Then pin RB4/SCK/SCL should be enabled by  
setting bit, CKP.  
As a slave-transmitter, the ACK pulse from the master-  
receiver is latched on the rising edge of the ninth SCL  
input pulse. If the SDA line was high (not ACK), then  
TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS  
Status Bits as Data  
Transfer is Received  
Set bit SSPIF  
(SSP interrupt occurs if enabled)  
SSPSR SSPBUF  
Generate ACK Pulse  
BF  
SSPOV  
0
1
1
0
0
0
1
1
Yes  
No  
No  
No  
Yes  
No  
No  
No  
Yes  
Yes  
Yes  
Yes  
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.  
FIGURE 10-6:  
I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)  
Receiving Address  
R/W = 0  
Receiving Data  
Receiving Data  
ACK  
9
ACK  
9
ACK  
9
A7 A6 A5 A4  
SDA  
SCL  
A3 A2 A1  
D2  
D0  
8
D5  
D2  
D0  
8
D5 D4 D3  
D7 D6  
D1  
7
D7 D6  
D4 D3  
D1  
7
3
7
1
2
4
5
3
6
5
6
1
2
3
6
1
2
4
8
4
5
P
S
SSPIF (PIR1<3>)  
BF (SSPSTAT<0>)  
Cleared in software  
Bus master  
terminates  
transfer  
SSPBUF register is read  
SSPOV (SSPCON<6>)  
Bit SSPOV is set because the SSPBUF register is still full  
ACK is not sent  
FIGURE 10-7:  
I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)  
Receiving Address  
A7 A6 A5 A4 A3 A2 A1  
R/W = 1  
ACK  
Transmitting Data  
ACK  
SDA  
SCL  
D7 D6 D5 D4 D3 D2 D1 D0  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SCL held low  
while CPU  
responds to SSPIF  
Data is  
Sampled  
SSPIF (PIR1<3>)  
BF (SSPSTAT<0>)  
Cleared in software  
From SSP Interrupt  
Service Routine  
SSPBUF is written in software  
CKP (SSPCON<4>)  
Set bit after writing to SSPBUF  
(the SSPBUF must be written to  
before the CKP bit can be set)  
DS39598E-page 78  
2004 Microchip Technology Inc.