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PIC16F818-I/P 参数 Datasheet PDF下载

PIC16F818-I/P图片预览
型号: PIC16F818-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 二十零分之一十八引脚增强型闪存微控制器采用纳瓦技术 [18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 176 页 / 2941 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F818/819  
9.1.2  
TIMER1 MODE SELECTION  
9.1  
Capture Mode  
Timer1 must be running in Timer mode or Synchro-  
nized Counter mode for the CCP module to use the  
capture feature. In Asynchronous Counter mode, the  
capture operation may not work.  
In Capture mode, CCPR1H:CCPR1L captures the  
16-bit value of the TMR1 register when an event occurs  
on the CCP1 pin. An event is defined as:  
• Every falling edge  
• Every rising edge  
9.1.3  
SOFTWARE INTERRUPT  
• Every 4th rising edge  
• Every 16th rising edge  
When the Capture mode is changed, a false capture  
interrupt may be generated. The user should keep bit,  
CCP1IE (PIE1<2>), clear to avoid false interrupts and  
should clear the flag bit, CCP1IF, following any such  
change in operating mode.  
An event is selected by control bits, CCP1M3:CCP1M0  
(CCP1CON<3:0>). When a capture is made, the inter-  
rupt request flag bit, CCP1IF (PIR1<2>), is set. It must  
be cleared in software. If another capture occurs before  
the value in register CCPR1 is read, the old captured  
value is overwritten by the new captured value.  
9.1.4  
CCP PRESCALER  
There are four prescaler settings specified by bits  
CCP1M3:CCP1M0. Whenever the CCP module is  
turned off, or the CCP module is not in Capture mode,  
the prescaler counter is cleared. This means that any  
Reset will clear the prescaler counter.  
9.1.1  
CCP PIN CONFIGURATION  
In Capture mode, the CCP1 pin should be configured  
as an input by setting the TRISB<x> bit.  
Switching from one capture prescaler to another may  
generate an interrupt. Also, the prescaler counter will  
not be cleared; therefore, the first capture may be from  
Note 1: If the CCP1 pin is configured as an  
output, a write to the port can cause a  
capture condition.  
a
non-zero prescaler. Example 9-1 shows the  
2: The TRISB bit (2 or 3) is dependent upon  
the setting of configuration bit 12  
(CCPMX).  
recommended method for switching between capture  
prescalers. This example also clears the prescaler  
counter and will not generate the “false” interrupt.  
FIGURE 9-1:  
CAPTURE MODE  
OPERATION BLOCK  
DIAGRAM  
EXAMPLE 9-1:  
CHANGING BETWEEN  
CAPTURE PRESCALERS  
CLRF  
CCP1CON  
;Turn CCP module off  
MOVLW NEW_CAPT_PS ;Load the W reg with  
;the new prescaler  
Set Flag bit CCP1IF  
(PIR1<2>)  
Prescaler  
÷ 1, 4, 16  
;move value and CCP ON  
;Load CCP1CON with this  
;value  
MOVWF CCP1CON  
CCPR1H  
CCPR1L  
TMR1L  
CCP1 pin  
Capture  
Enable  
and  
Edge Detect  
TMR1H  
CCP1CON<3:0>  
Q’s  
DS39598E-page 66  
2004 Microchip Technology Inc.