欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F818-I/P 参数 Datasheet PDF下载

PIC16F818-I/P图片预览
型号: PIC16F818-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 二十零分之一十八引脚增强型闪存微控制器采用纳瓦技术 [18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 176 页 / 2941 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F818-I/P的Datasheet PDF文件第138页浏览型号PIC16F818-I/P的Datasheet PDF文件第139页浏览型号PIC16F818-I/P的Datasheet PDF文件第140页浏览型号PIC16F818-I/P的Datasheet PDF文件第141页浏览型号PIC16F818-I/P的Datasheet PDF文件第143页浏览型号PIC16F818-I/P的Datasheet PDF文件第144页浏览型号PIC16F818-I/P的Datasheet PDF文件第145页浏览型号PIC16F818-I/P的Datasheet PDF文件第146页  
PIC16F818/819  
TABLE 15-8: I2C™ BUS DATA REQUIREMENTS  
Param.  
Symbol  
Characteristic  
Min  
Max Units  
Conditions  
No.  
100*  
THIGH  
Clock High Time  
100 kHz mode  
4.0  
0.6  
µs  
µs  
400 kHz mode  
SSP Module  
100 kHz mode  
400 kHz mode  
SSP Module  
1.5 TCY  
4.7  
101*  
TLOW  
Clock Low Time  
µs  
µs  
1.3  
1.5 TCY  
102*  
103*  
TR  
TF  
SDA and SCL Rise 100 kHz mode  
Time  
1000  
ns  
ns  
400 kHz mode  
20 + 0.1 CB 300  
CB is specified to be from  
10-400 pF  
SDA and SCL Fall 100 kHz mode  
Time  
300  
ns  
ns  
400 kHz mode  
20 + 0.1 CB 300  
CB is specified to be from  
10-400 pF  
90*  
TSU:STA  
THD:STA  
Start Condition  
Setup Time  
100 kHz mode  
400 kHz mode  
4.7  
0.6  
4.0  
0.6  
0
µs  
µs  
µs  
µs  
ns  
µs  
ns  
ns  
µs  
µs  
ns  
ns  
µs  
µs  
Only relevant for Repeated  
Start condition  
91*  
Start Condition Hold 100 kHz mode  
Time  
After this period, the first  
clock pulse is generated  
400 kHz mode  
106*  
107*  
92*  
THD:DAT Data Input Hold  
Time  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
0
0.9  
TSU:DAT  
TSU:STO  
TAA  
Data Input Setup  
Time  
250  
100  
4.7  
0.6  
(Note 2)  
Stop Condition  
Setup Time  
109*  
110*  
Output Valid from  
Clock  
3500  
(Note 1)  
TBUF  
Bus Free Time  
4.7  
1.3  
Time the bus must be free  
before a new transmission  
can start  
CB  
Bus Capacitive Loading  
400  
pF  
*
These parameters are characterized but not tested.  
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region  
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.  
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system but  
the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does  
not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL  
signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns  
(according to the Standard mode I2C bus specification), before the SCL line is released.  
DS39598E-page 140  
2004 Microchip Technology Inc.