PIC16F631/677/685/687/689/690
4.2.5.4
RA3/MCLR/VPP
4.2.5.5
RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The
RA3/MCLR/VPP pin is configurable to function as one
of the following:
Figure 4-5 shows the diagram for this pin. The
RA4/AN3/T1G/OSC2/CLKOUT pin is configurable to
function as one of the following:
• a general purpose input
• a general purpose I/O
• as Master Clear Reset with weak pull-up
• an analog input for the ADC (except PIC16F631)
• a TMR1 gate input
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
• a crystal/resonator connection
• a clock output
VDD
MCLRE
Weak
FIGURE 4-5:
BLOCK DIAGRAM OF RA4
Data Bus
Analog(3)
Input Mode
MCLRE
Reset
Input
Pin
CLK(1)
Modes
VDD
Data Bus
D
RD
TRISA
VSS
Q
Q
MCLRE
VSS
WR
CK
RD
PORTA
Weak
WPUA
D
Q
Q
RABPU
RD
WPUA
Q
Q
D
CK
WR
IOCA
Oscillator
Circuit
Q3
OSC1
EN
VDD
CLKOUT
Enable
RD
IOCA
D
FOSC/4
1
0
D
Q
Q
EN
Interrupt-on-
Change
I/O Pin
WR
CK
PORTA
CLKOUT
Enable
RD PORTA
VSS
D
Q
Q
INTOSC/
RC/EC(2)
WR
TRISA
CK
CLKOUT
Enable
RD
TRISA
Analog
Input Mode
RD
PORTA
D
Q
Q
Q
D
D
CK
WR
IOCA
Q3
EN
RD
IOCA
Q
EN
Interrupt-on-
Change
RD PORTA
To T1G
To A/D Converter(4)
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: ANSEL determines Analog Input mode.
4: Not implemented on PIC16F631.
DS41262D-page 66
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
