PIC16F631/677/685/687/689/690
FIGURE 3-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
POR, BOR
(1)
Resets
(2)
CONFIG
CPD
—
CP
IRCF2
—
MCLRE PWRTE
WDTE
OSTS
TUN3
SSPIE
SSPIF
FOSC2
HTS
FOSC1
LTS
FOSC0
SCS
—
—
OSCCON
OSCTUNE
PIE1
IRCF1
—
IRCF0
TUN4
TXIE
-110 x000 -110 x000
---0 0000 ---u uuuu
—
TUN2
TUN1
TUN0
—
ADIE
ADIF
RCIE
RCIF
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PIR1
—
TXIF
Legend:
x= unknown, u= unchanged, – =unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (Register 14-1) for operation of all register bits.
DS41262D-page 58
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
